The SST Fully-Synchronous Multi-GHz Analog Waveform Recorder with Nyquist-Rate Bandwidth and Flexible Trigger Capabilities

The design and performance of a fully-synchronous multi-GHz analog transient waveform recorder I.C. ("SST") with fast and flexible trigger capabilities is presented. The SST's objective is to provide multi-GHz sample rates with intrinsically-stable timing, Nyquist-rate sampling and high trigger bandwidth, wide dynamic range and simple operation. Containing 4 channels of 256 samples per channel, the SST is fabricated in an inexpensive 0.25 micrometer CMOS process and uses a high-performance package that is 8 mm on a side. It has a 1.9V input range on a 2.5V supply, exceeds 12 bits of dynamic range, and uses ~128 mW while operating at 2 G-samples/s and full trigger rates. With a standard 50 Ohm input source, the SST exceeds ~1.5 GHz -3 dB bandwidth. The SST's internal sample clocks are generated synchronously via a shift register driven by an external LVDS oscillator running at half the sample rate (e.g., a 1 GHz oscillator yields 2 G-samples/s). Because of its purely-digital synchronous nature, the SST has ps-level timing uniformity that is independent of sample frequencies spanning over 6 orders of magnitude: from under 2 kHz to over 2 GHz. Only three active control lines are necessary for operation: Reset, Start/Stop and Read-Clock. When operating as common-stop device, the time of the stop, modulo 256 relative to the start, is read out along with the sampled signal values. Each of the four channels integrates dual-threshold trigger circuitry with windowed coincidence features. Channels can discriminate signals with ~1mV RMS resolution at >600 MHz bandwidth.Comment: 3 pages, 6 figures, 1 table, submitted for publication in the Conference Record of the 2014 IEEE Nuclear Science Symposium, Seattle, WA, November 201

A Multi-Gigahertz Analog Transient Recorder Integrated Circuit

A monolithic multi-channel analog transient recorder, implemented using switched capacitor sample-and-hold circuits and a high-speed analogically-adjustable delay-line-based write clock, has been designed, fabricated and tested. The 2.1 by 6.9 mm layout, in 1.2 micron CMOS, includes over 31,000 transistors and 2048 double polysilicon capacitors. The circuit contains four parallel channels, each with a 512 deep switched-capacitor sample-and-hold system. A 512 deep edge sensitive tapped active delay line uses look-ahead and 16 way interleaving to develop the 512 sample and hold clocks, each as little as 3.2 ns wide and 200 ps apart. Measurements of the device have demonstrated 5 GHz maximum sample rate, at least 350 MHz bandwidth, an extrapolated rms aperture uncertainty per sample of 0.7 ps, and a signal to rms noise ratio of 2000:1.Comment: 64 pages, 17 figures. Thesis, University of California, Berkeley, 199

The SST Multi-G-Sample/s Switched Capacitor Array Waveform Recorder with Flexible Trigger and Picosecond-Level Timing Accuracy

The design and performance of a multi-G-sample/s fully-synchronous analog transient waveform recorder I.C. ("SST") with fast and flexible trigger capabilities is presented. Containing 4 channels of 256 samples per channel and fabricated in a 0.25 {\mu}m CMOS process, it has a 1.9V input range on a 2.5V supply, achieves 12 bits of dynamic range, and uses ~160 mW while operating at 2 G-samples/s and full trigger speeds. With a standard 50 Ohm input source, the SST's analog input bandwidth is ~1.3 GHz within about +/-0.5 dB and reaches a -3 dB bandwidth of 1.5 GHz. The SST's internal sample clocks are generated synchronously via a shift register driven by an external LVDS oscillator, interleaved to double its speed (e.g., a 1 GHz clock yields 2 G-samples/s). It can operate over 6 orders of magnitude in sample rates (2 kHz to 2 GHz). Only three active control lines are necessary for operation: Reset, Start/Stop and Read-Clock. Each of the four channels integrates dual-threshold discrimination of signals with ~1 mV RMS resolution at >600 MHz bandwidth. Comparator results are directly available for simple threshold monitoring and rate control. The High and Low discrimination can also be AND'd over an adjustable window of time in order to exclusively trigger on bipolar impulsive signals. Trigger outputs can be CMOS or low-voltage differential signals, e.g. 1.2V CMOS or positive-ECL (0-0.8V) for low noise. After calibration, the imprecision of timing differences between channels falls in a range of 1.12-2.37 ps sigma at 2 G-samples/s.Comment: 9 pages, 16 figures, 1 tabl

Design and Performance of the Data Acquisition System for the NA61/SHINE Experiment at CERN

This paper describes the hardware, firmware and software systems used in data acquisition for the NA61/SHINE experiment at the CERN SPS accelerator. Special emphasis is given to the design parameters of the readout electronics for the 40m^3 volume Time Projection Chamber detectors, as these give the largest contribution to event data among all the subdetectors: events consisting of 8bit ADC values from 256 timeslices of 200k electronic channels are to be read out with ~100Hz rate. The data acquisition system is organized in "push-data mode", i.e. local systems transmit data asynchronously. Techniques of solving subevent synchronization are also discussed.Comment: 14 pages, 13 figure

Radar absorption, basal reflection, thickness and polarization measurements from the Ross Ice Shelf, Antarctica

Radio-glaciological parameters from the Moore’s Bay region of the Ross Ice Shelf, Antarctica, have been measured. The thickness of the ice shelf in Moore’s Bay was measured from reflection times of radio-frequency pulses propagating vertically through the shelf and reflecting from the ocean, and is found to be 576 ± 8 m. Introducing a baseline of 543 ± 7m between radio transmitter and receiver allowed the computation of the basal reflection coefficient, R, separately from englacial loss. The depth-averaged attenuation length of the ice column, 〈L〉 is shown to depend linearly on frequency. The best fit (95% confidence level) is 〈L(ν)〉= (460±20) − (180±40)ν m (20 dB km−1), for the frequencies ν = [0.100–0.850] GHz, assuming no reflection loss. The mean electric-field reflection coefficient is (1.7 dB reflection loss) across [0.100–0.850] GHz, and is used to correct the attenuation length. Finally, the reflected power rotated into the orthogonal antenna polarization i

Novel integrated CMOS pixel structures for vertex detectors

Novel CMOS active pixel structures for vertex detector applications have been designed and tested. The overriding goal of this work is to increase the signal to noise ratio of the sensors and readout circuits. A large-area native epitaxial silicon photogate was designed with the aim of increasing the charge collected per struck pixel and to reduce charge diffusion to neighboring pixels. The photogate then transfers the charge to a low capacitance readout node to maintain a high charge to voltage conversion gain. Two techniques for noise reduction are also presented. The first is a per-pixel kT/C noise reduction circuit that produces results similar to traditional correlated double sampling (CDS). It has the advantage of requiring only one read, as compared to two for CDS, and no external storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5, to 12.8 e{sup -}. Finally, a column-level active reset technique is explored that suppresses kT/C noise during pixel reset. In tests, noise was reduced by a factor of 7.6 times, to an estimated 5.1 e{sup -} input-referred noise. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21 in our tests. The latter feature may possibly reduce pixel-by-pixel pedestal differences to levels low enough to permit sparse data scan without per-pixel offset corrections